The testbench can seamlessly integrate with an existing design, and enables the revealing of metastability triggered issues during RTL simulation.ĪLINT-PRO is equipped with CDC and RDC Viewers designed to facilitate analysis of metastability issues.
Multiclock domain synchronization verification#
Static checks are implemented in the form of linting and are performed in ALINT-PRO, while dynamic verification is based on integration with Riviera-PRO™, Active-HDL™, or ModelSim® through an automatically generated SystemVerilog or VHDL testbench. The CDC/RDC verification strategy is comprised of three key elements: static structural verification, design constraints setup, and dynamic functional verification. Still, it is very important to clean both classes of domain crossing issues, and the verification methods for both types of issues have a lot in common. The root-cause are the unsynchronized data transfers between sequential elements that have different unrelated asynchronous reset signals, even if they are controlled with an identical clock.Īs a rule of thumb, CDC bugs have a higher probability than RDC bugs, as RDC-related metastability can only happen during a reset event, while CDC-related metastability may occur at any point in time. Reset Domain Crossing (RDC) issues represent a relatively new class of errors, which are typical for designs with complex reset strategies having dynamically switchable parts, and thus, they require more frequent reset sequences within certain regions of the design. The number of independent interacting clocks, and their associated mistakes, in designs is continuously growing in most industries. Included rules uncover critical problems during the RTL Design and Functional Verification stages, significantly cutting down time to market.Ĭlock Domain Crossing (CDC) issues constitute a complex and widely spread verification problem for the majority of modern designs, regardless of the application type or implementation technology. Tool Assessment and Qualification ProcessĪLINT-PRO™ features an ALDEC_CDC rule plug-in that focuses on clock and reset domain crossings analysis as well as the handling of metastability issues in complex, modern multi-clock and multi-reset designs.
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